In order to effectively protect internal circuits and to minimize the parasitic effects of CMOS input/output (I/O) electrostatic discharge (ESD) protection circuits, the dual-diode ESD protection has been widely adopted for effective on-chip ESD protection.
As IC dimensions are reduced with advancing technology, ESD protection devices will continue to become smaller and smaller. In order to take advantage of the dimension reductions without excessive diminishing of ESD performance, many diode structure design approaches have been proposed. For example, change the length of the diode structure, the width of the doping regions, the depth or spacing of the shallow trench isolation (STI), and other approaches. However, the ESD failure current increases with increases in the length of the diode structure, the width of the doping regions.
Therefore, a diode structure with highly robust ESD protection for high-speed I/O applications is desired.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.